A split-gate type non-volatile memory transistor and a stacked type non-volatile memory transistor are known as those of the devices that are applied to an electrically erasable programmable ROM (EEPROM). One example of a semiconductor device including a split-gate type non-volatile memory transistor will be described below. FIG. 18 schematically shows a cross-sectional view of one example of a conventional semiconductor device including a split-gate type non-volatile memory transistor.
A split-gate type memory transistor 300 has, in the case of an N-type transistor as an example, a source region 14 and a drain region 16 composed of N+-type impurity diffusion layers formed in a silicon substrate 10 of P-type, and a first dielectric layer 70 as a gate insulation layer formed on a surface of the silicon substrate 10. A floating gate 72, a second dielectric layer 76 and a control gate 78 are successively formed on the first dielectric layer 70.
A third dielectric layer 74 is formed on the floating gate 72. The third dielectric layer 74 is composed of a dielectric layer that is formed by selectively oxidizing part of a polysilicon layer that becomes to be the floating gate 72. In other words, the third dielectric layer 74 has a structure in which the film thickness thereof becomes thinner from its center toward both of its end sections, as shown in FIG. 18. As a result, upper edge sections 720 of the floating gate 72 form sharp edges, such that an electric field concentration is apt to occur at the upper edge sections 720. An interlayer dielectric layer 240 is formed on the silicon substrate 10. The interlayer dielectric layer 240 is generally composed only of a silicon oxide layer. A through hole 246 is formed in a specified region of the interlayer dielectric layer 240. The through hole 246 is filled with a conductive material to form a contact layer 32. A wiring layer 30 that is electrically connected to the contact layer 32 is formed on the interlayer dielectric layer 240.
For the operation of the memory transistor with a split-gate structure 300, a channel current is flown between the source region 14 and the drain region 16 to thereby inject a charge (hot electrons) in the floating gate 72 as indicated by an arrow A10 when data is written. When data is erased, a predetermined high voltage is applied to the control gate 78 to thereby transfer the charge stored in the floating gate 72 through the second dielectric layer 76 to the control gate 78 as indicated by an arrow B10 by Fowler-Nordheim tunneling conduction (FN conduction).
It is an object of the present invention to provide a semiconductor device having a non-volatile memory transistor in which the characteristic stability of the non-volatile memory transistor is improved, and also a method for manufacturing the same.
[Disclosure of The Invention]
A semiconductor device in accordance with a first embodiment of the present invention includes a non-volatile memory transistor, and an interlayer dielectric layer provided on a semiconductor layer in which the non-volatile memory transistor is formed, wherein the interlayer dielectric layer is an insulation layer for electrically isolating the non-volatile memory transistor from a conductive layer formed over the semiconductor layer, and the interlayer dielectric layer includes a layer containing nitride.
In the semiconductor device in accordance with the first embodiment of the present invention, the interlayer dielectric layer includes a layer containing nitride. For this reason, the non-volatile memory transistor can be protected from process induced charges that are generated in various manufacturing steps after the interlayer dielectric layer has been formed. As a result, for example, FTV (Forward Tunnel Voltage), FTUR (Forward Trap Up Rate) and the rewritable number (Endurance) characteristic of the non-volatile memory transistor can be improved.
In the semiconductor device in accordance with embodiments of the present invention, preferably, the layer containing nitride may take at least one of the following embodiments 1) and 2).
1) The layer containing nitride can assume an embodiment in which the layer containing nitride is provided as a lowermost layer of the interlayer dielectric layer, an embodiment in which the same is provided as an uppermost layer of the interlayer dielectric layer, or an embodiment in which the same is provided as an intermediate layer of the interlayer dielectric layer.
2) The nitride may be at least one of silicon nitride and silicon oxide nitride.
In the semiconductor device in accordance with embodiments of the present invention, more preferably, the layer containing nitride may take at least one of the following embodiments 1) and 2).
1) An embodiment in which the non-volatile memory transistor includes a floating gate disposed over the semiconductor layer through a gate dielectric layer, a tunneling dielectric layer that contacts at least a part of the floating gate, a control gate that is formed over the tunneling dielectric layer, and source region and drain region formed in the semiconductor layer.
2) An embodiment in which the non-volatile memory transistor includes a floating gate disposed over the semiconductor layer through a gate dielectric layer, a control gate disposed over the floating gate through an intermediate dielectric layer, and source region and drain region formed in the semiconductor layer.
A semiconductor device in accordance with another embodiment of the present invention is a semiconductor device that includes a non-volatile memory transistor formed on a semiconductor layer, and includes an interlayer dielectric layer provided over the semiconductor layer and the non-volatile memory transistor, wherein the interlayer dielectric layer includes an oxide film provided as a lowermost layer of the interlayer dielectric layer and a layer containing nitride provided on the oxide film.
In the embodiment of the present invention, the oxide film may preferably have a thickness of 10-80 nm. Furthermore, due to the fact that the thickness of the oxide film is in a range of 30-70 nm, the characteristics required in view of the rewritable number can be secured, and the memory characteristic can be stabilized by suppressing the amount of changes in the threshold voltage of the control gate.
In accordance with an embodiment of the present invention, more preferably, the oxide film may be an oxide film that is formed by a reduced pressure CVD method using TEOS.
A method for manufacturing a semiconductor device in accordance with an embodiment of the present invention includes the following steps.    (a) A step of forming a non-volatile memory transistor in a semiconductor layer, and    (b) A step of forming an interlayer dielectric layer over the semiconductor layer in which the non-volatile memory transistor,    wherein the interlayer dielectric layer is an insulation layer for electrically isolating a conductive layer formed over the semiconductor layer from the non-volatile memory transistor, and the interlayer dielectric layer includes a layer containing nitride.
In the method for manufacturing a semiconductor device in accordance with the embodiment of the present invention, the layer containing nitride and the non-volatile memory transistor can assume embodiments that are the same as those of the semiconductor device in accordance with the embodiment of the present invention.
Here, the “semiconductor layer” described above includes a semiconductor substrate and a semiconductor layer formed on a substrate.